advance information 128k x 24 static ram cy7c1024av33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 may 1, 2000 33 features ? high speed ?t aa = 9 ns cmos for optimum speed/power center power/ground pinout automatic power-down when deselected easy memory expansion with ce1 , ce2, ce3 and oe options functional description the cy7c1024av33 is a high-performance cmos static ram organized as 131,072 words by 24 bits. easy memory expan- sion is provided by an active low ce1 , ce3 , active high ce2, an active low output enable (oe ), and three-state driv- ers. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce1 , ce2, ce3 ) active and write enable (we ) inputs low. data on the 24 i/o pins (i/o 0 through i/o 23 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce1 , ce2, ce3 ) active and output enable (oe ) low while forcing write enable (we ) high. under these condi- tions, the contents of the memory location specified by the address pins will appear on the i/o pins. the 24 input/output pins (i/o 0 through i/o 23 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce1 , ce3 low, ce2 high, and we low). the cy7c1024av33 is available in a standard 119-ball bga package and a 100-pin tqfp package. functional block diagram ce# address buffer row decoder column decoder memory array 128k x 24 i/o buffer dq0 control a16 a0 dq23 v cc v ss ce1# ce2 be0# be1# be2# we# oe# selection guide 7c1024av33-9 7c1024av33-10 7c1024av33-12 7c1024av33-15 maximum access time (ns) 9 10 12 15 maximum operating current (ma) 300 275 250 225 maximum standby current (ma) 15 15 15 15
cy7c1024av33 advance information 2 pin configurations 119 bga top view 1234567 a ncaaaaanc b nc a a ce1 aanc c dq nc ce2 nc ce3 nc dq d dq v dd v ss v ss v ss v dd dq e dq v ss v dd v ss v dd v ss dq f dq v dd v ss v ss v ss v dd dq g dq v ss v dd v ss v dd v ss dq h dq v dd v ss v ss v ss v dd dq j nca v ss v dd v ss v dd v ss nc k dq v dd v ss v ss v ss v dd dq l dq v ss v dd v ss v dd v ss dq m dq v dd v ss v ss v ss v dd dq n dq v ss v dd v ss v dd v ss dq p dq v dd v ss v ss v ss v dd dq r dq nc nc nc nc nc dq t nc a a we aanc u nc a a oe aanc
cy7c1024av33 advance information 3 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage on v cc to relative gnd [1] .... ? 0.5v to +7.0v dc voltage applied to outputs in high z state [1] .................................... ? 0.5v to v cc + 0.5v dc input voltage [1] ................................. ? 0.5v to v cc + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. t a is the ? instant on ? case temperature. 100-pin tqfp top view pin configurations (continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 41 42 43 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 nc nc a11 a3 nc nc ce# a4 nc nc vss ce1# a16 a5 vcc nc vcc vss vss vcc dq4 dq5 dq6 dq7 vcc vss dq8 dq9 vcc nc nc vss nc nc nc a10 a9 a8 vss vcc a0 be1# be0# a2 a1 nc a7 oe# we# a6 be2# nc a12 a13 a14 a15 ce2 dq0 dq1 vss vcc dq2 dq3 vcc vss vcc vss nc dq10 dq11 nc vcc vss vss vcc dq20 dq21 dq22 dq23 vcc vss dq12 dq13 vss vcc nc nc dq16 dq17 vss vcc dq18 dq19 vcc vss vcc vss nc dq14 dq15 operating range range ambient temperature [2] v cc commercial 0 c to +70 c 3.3v 10% industrial ? 40 c to +85 c 3.3v 10%
cy7c1024av33 advance information 4 electrical characteristics over the operating range parameter description test conditions [3] 1024av33-9 1024av33-10 1024av33-12 1024av33-15 min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 3+3 ? 3+3 ? 3+3 ? 3+3 a i oz output leakage current gnd < v i < v cc , output disabled ? 5+5 ? 5+5 ? 5+5 ? 5+5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 300 275 250 225 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 60 60 60 60 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 15 15 15 15 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 8 pf notes: 3. ce is a combination of ce1 , ce2 and ce3 4. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms 1024v33 ? 3 1024v33 ? 4 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope 3.3v output 5 pf including jig and scope (a) (b) 3 ns 3 ns output r1 480 ? r1 480 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th
cy7c1024av33 advance information 5 switching characteristics [5] over the operating range 7c1024av33-9 7c1024av33-10 7c1024av33-12 7c1024av33-15 parameter description [3] min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 9 10 12 15 ns t aa address to data valid 9 10 12 15 ns t oha data hold from address change 3 3 3 3 ns t ace ce active to data valid 9 10 12 15 ns t doe oe low to data valid 4 5 6 7 ns t lzoe oe low to low z 0 0 0 0 ns t hzoe oe high to high z [6, 7] 4566ns t lzce ce active to low z [7] 3333ns t hzce ce inactive to high z [6, 7] 5566ns t pu ce active to power-up 0 0 0 0 ns t pd ce inactive to power-down 9 10 12 15 ns write cycle [8, 9] t wc write cycle time 9 10 12 15 ns t sce ce active to write end 8 8 9 9 ns t aw address set-up to write end 7 7 8 8 ns t ha address hold from write end 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 ns t pwe we pulse width 7 7 8 8 ns t sd data set-up to write end 5 5 6 6 ns t hd data hold from write end 0 0 0 0 ns t lzwe we high to low z [7] 3333ns t hzwe we low to high z [6, 7] 5566ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal t hat terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1024av33 advance information 6 switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 (oe controlled) [3, 11, 12] write cycle no. 1 (ce controlled) [3, 13, 14] notes: 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. previous data valid data valid t rc t aa t oha 1024v33 ? 6 address data out 1024v33 ? 7 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o 1024v33 ? 8
cy7c1024av33 advance information 7 write cycle no. 2 (we controlled, oe high during write) [13, 14] write cycle no. 3 (we controlled, oe low) [3, 14] note: 15. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) 1024v33 ? 9 t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 15 1024v33 ? 10 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 15
cy7c1024av33 advance information 8 document #: 38-00983-** truth table ce1 ce2 ce3 oe we i/o 0 ? i/o 23 mode power h x x x x high z power-down standby (i sb ) x l x x x high z power-down standby (i sb ) x x h x x high z power-down standby (i sb ) l h l l h data out read active (i cc ) l h l x l data in write active (i cc ) l h l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 9 cy7c1024av33-9ac a101 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) commercial CY7C1024AV33-9BGC bg119 119-ball bga 10 cy7c1024av33-10ac a101 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) cy7c1024av33-10bgc bg119 119-ball bga 12 cy7c1024av33-12ac a101 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) cy7c1024av33-12bgc bg119 119-ball bga 15 cy7c1024av33-15ac a101 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) cy7c1024av33-15bgc bg119 119-ball bga cy7c1024av33-15bgi bg119 119-ball bga industrial
cy7c1024av33 advance information 9 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1024av33 advance information ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 119-lead fbga (14 x 22 x 2.4 mm) bg119 51-85115
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